Process Design Kits (PDK)
TowerJazz PDK’s offer a front-to-back integrated custom design environment that supports all major EDA vendors’ design flows. Our design kits contain the parameters such as layer thickness and stress gradient that have been well defined within the tolerances of our specific manufacturing processes. The kit automatically sets these constraints for the designer allowing only those parameters to be varied during the evaluation of designs and allowing only those designs that are perfectly compatible with the manufacturing process.
TowerJazz Supported EDA PDK Flows by Technology — Migdal Haemek
180nm: TS18, TS18PM & TS35PM
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | P&R support | P&R support | P&R support | |
| DRC | DRC | DRC | ||
| LVS | LVS | LVS | ||
| PEX | PEX | PEX | ||
| iPDK | P-Cell Library | iPDK | iPDK | P-Cell Library |
1.0μm: TS100 — Power Management (700V)
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| DRC | |||
| LVS | |||
| PEX | |||
| P-Cell Library |
130nm: TS13
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | P&R support | P&R support | P&R support |
| DRC | DRC | DRC | |
| LVS | LVS | LVS | |
| PEX: 5 Corner, Erosion | PEX: 5 Corner, Erosion | PEX: 5 Corner, Erosion | |
| DFM Utilities | DFM Utilities | ||
| P-Cell Library |
0.6μm: TS60
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | P&R support | ||
| DRC | |||
| LVS | |||
| PEX | |||
| P-Cell Library |
0.35μm: TS35
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | P&R support | ||
| DRC | |||
| LVS | |||
| PEX |
TowerJazz Supported EDA PDK Flows by Technology — Newport Beach
0.35μm: BC35 — Si BiCMOS
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | |||
| DRC | DRC | ||
| LVS | LVS | ||
| PEX | PEX | ||
| P-Cell Library |
0.35μm: SBC35 — SiGe BiCMOS
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | P&R support | |||
| DRC | DRC | DRC | ||
| LVS | LVS | LVS | ||
| PEX | PEX | PEX | ||
| P-Cell Library | P-Cell Library |
0.25μm: BCD25 — Power Management
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | P&R support | |||
| DRC | DRC | DRC | ||
| LVS | LVS | LVS | ||
| PEX | PEX | PEX | ||
| P-Cell Library | P-Cell Library |
0.25μm: CA25 — Digital and RF CMOS
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | |||
| DRC | DRC | ||
| LVS | LVS | ||
| PEX | PEX | ||
| P-Cell Library |
0.18μm: CA18 — RF CMOS
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | P&R support | |||
| DRC | DRC | DRC | ||
| LVS | LVS | LVS | ||
| PEX | PEX | PEX | ||
| P-Cell Library | P-Cell Library | P-Cell Library |
0.18μm: SBC18 — SiGe BiCMOS
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | P&R support | |||
| DRC | DRC | DRC | ||
| LVS | LVS | LVS | ||
| PEX | PEX | PEX | ||
| P-Cell Library | P-Cell Library | P-Cell Library |
0.13μm: SBC13, SBL13 — SiGe BiCMOS
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| SPICE Model | SPICE Model | SPICE Model | SPICE Model |
| P&R support | |||
| DRC | DRC | ||
| LVS | LVS | ||
| PEX | PEX | ||
| P-Cell Library |
Our Process Design Kits contain:
- Symbols and schematics
- Advanced scalable Models with RF accuracy
- PSP for MOSFETs
- HICUM for BJTs
- R3 resistors
- MOS Model 20 for LDMOS devices
- Monte Carlo Statistical and Mismatch Simulation Capability
- Scalable layout cells (Pcells) with time saving and features targeted for end applications and tightly coupled to the model
- An industry first scalable drift length LDMOS
- Scalable inductors
- Extensive Enhanced Layout Utilities to speed layout cycle time
- Parasitic Extraction and Back-Annotation integrated with model and layout features
Modeling tools that are also included with our PDK’s
PCMT: Process Control Monitoring Model Tool that allows you to evaluate wafer or die specific performance in your simulation environment
X-Sigma: A unique process variation modeling tool that allows design teams to trade off yield vs performance and efficiently perform design sensitivity analysis
RMT: A Reliability Modeling Tool is offered in the Silicon Germanium BiCMOS (SBC) family of technologies, enabling users to predict chip operation as a function of operating conditions and age
JIT: The Jazz Inductor Toolbox is a searchable inductor database with automated instantiation of schematic and layout of highly optimized inductors. Support of square and octagonal inductors with and without shields is included
PADL: A pre-characterized Power Amplifier Design Library accelerates SiGe PA design to market through off the shelf power cells and PA-centric technology
